1. Field of the Invention
The present invention relates to a motor driving circuit.
2. Description of the Related Art
In recent years, synchronous rectification that brings power efficiency higher than diode rectification has been receiving much attention in the field of motor driving circuit. Synchronous rectification means a rectification method that is carried out with focusing on low on-resistance of a field effect MOS transistor. According to the method, a field effect MOS transistor energizing a driving coil is utilized as a rectification element in synchronization with PWM drive (e.g., see Japanese Patent Application Laid-Open Publication No. 2002-272162). An operation of synchronous rectification will hereinafter be described.
An H-bridge circuit, as shown in FIG. 9, is configured such that one terminal of a driving coil L is connected to a connection point A at which a source side transistor T1 is connected to a sink side transistor T2, while the other terminal of the driving coil L is connected to a second connection point B at which a source side transistor T3 is connected to a sink side transistor T4.
When feeding a coil current IL through the driving coil L so as to flow from the connection point A toward the connection point B, the source side transistor T3 and the sink side transistor T2 is turned off. The source side transistor T1 is kept turned on constantly (saturation drive), and the sink side transistor T4 is turned on and off by a PWM signal having a duty ratio corresponding to motor rotation speed. When the PWM signal applied to a gate electrode of the sink side transistor T4 becomes H level to turn on the sink side transistor T4, the coil current IL flows through a power line, a drain-source path of the source side transistor T1, the connection point A, the driving coil L, the connection point B, the drain-source path of the sink side transistor T4, and a ground line in the order presented above, as shown in FIG. 9.
Then, when the PWM signal applied to the gate electrode of the sink side transistor T4 changes in level from H level to L level, that is, when the sink side transistor T4 changes in state from on to off, the driving coil L tries to maintain a direction of the coil current IL when the sink side transistor T4 is on (direction of the flow from the connection point A to the connection point B) because of inherent characteristics of the driving coil L.
In a field effect MOS transistor, a parasitic diode is present between the drain and the source of the field effect MOS transistor as a structural consequence. For example, between the drain and the source of the source side transistor T1, there is present a parasitic diode DA with an anode thereof being connected to the drain and a cathode thereof being connected to the source. Likewise, between the drain and the source of the source side transistor T3, there is present a parasitic diode DB with the anode thereof being connected to the drain and the cathode thereof being connected to the source.
Because of this, when the PWM signal applied to the gate electrode of the sink side transistor T4 changes in level from H-level to L-level, a regenerative current IL′ flows through the power line, the drain-source path of the source side transistor T1, the connection point A, the driving coil L, the contact point B, and the parasitic diode DB of the source side transistor T3 in the above order. As a result, in the parasitic diode DB, there is consumed unnecessary power given by the product of a forward voltage VF and the regenerative current IL′ (forward current).
To prevent this, the source side transistor T3 is forcibly turned on in synchronization with timing of change in state from on to off of the sink side transistor T4, as shown in FIG. 10. This causes large portion of the regenerative current IL′ to flow through the source-drain path of the source side transistor T3 having on-resistance lower than that of the parasitic diode DB. Thus, power consumption in the parasitic diode DB is suppressed. Similarly, in the parasitic diode DA, the source side transistor T1 having on-resistance lower than that of the parasitic diode DA is forcibly turned on in synchronization with timing of change in state from on to off of the sink side transistor T2.
When both of the source side transistors T1 and T3 are turned on to cause the regenerative current IL′ to flow in the direction from the connection point A toward the connection point B, as shown in FIG. 10, a coil voltage is generated at the driving coil L. Therefore, in order to cancel the coil voltage generated at the driving coil L, a consumption current IL″ flows, in a direction opposite to the regenerative current IL′, through the power line, the drain-source path of the source side transistor T3, the connection point B, the driving coil L, the connection point A, and the source-drain path of the source side transistor T1 in the above order, as shown in FIG. 11.
Then, the PWM signal applied to the gate electrode of the sink side transistor T4 changes again in level from L-level to H-level and the source side transistor T3, which is a subject of synchronous rectification, changes in level from on to off. When the consumption current IL″ (see FIG. 11) attenuates as the source side transistor T3 changes in level from on to off, a backflow current IL′″ (see FIG. 12) does not flow in a direction from the ground line toward the power line. If the consumption current IL″ (see FIG. 11) attenuates incompletely and partly survives as the source side transistor T3 changes in level from on to off, the backflow current IL′″ (see FIG. 12) in the same direction as that of the consumption current IL″ flows through the ground line, the source-drain path of the sink side transistor T4, the connection point B, the driving coil L, the connection point A, the source-drain path of the source side transistor T1, and the power line in the above order. As a result of this, a level of a source voltage VCC becomes higher than a specification value, which may, at worst, result in a destruction of the motor driving circuit.
This backflow phenomenon in which the backflow current IL′″ flows from the ground line toward the power line tends to occur when on-duty of the PWM signal is low. When the on-duty of the PWM signal is high, amplitude of a sine wave coil voltage EMF generated at the driving coil L is substantially identical with the amplitude of the source voltage VCC. Since the size of the coil current IL flowing through the driving coil L is in proportion to a level difference between the source voltage VCC and the coil voltage EMF, the coil current IL becomes small in amount in this case. When the on-duty of the PWM signal is low, the amplitude of the coil voltage EMF becomes small to increase a level difference between the source voltage VCC and the coil voltage EMF, so that the coil current IL is increased in amount.
When the on-duty of the PWM signal is high, the coil current IL is small in amount, so that the consumption current IL″ (see FIG. 11) attenuates. It therefore becomes hard for the backflow current IL′″ (see FIG. 12) to flow. On the other hand, when the on-duty of the PWM signal is low, the coil current IL is great in amount, so that the consumption current IL″ (see FIG. 11) survives. Therefore the flow of the backflow current IL′″ (see FIG. 12) is facilitated. That is, when lowering the on-duty of the PWM signal, the backflow current IL′″ (see FIG. 12) that may destroy the motor driving circuit flows easily.